Recessed channel negative differential resistance-based memory cell

ABSTRACT

Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh.

FIELD OF THE INVENTION

This invention relates to recessed thyristor-based memory cell design for an integrated circuit.

BACKGROUND

Many different types of memory cell designs exist in the integrated circuitry art, each with its own advantages and disadvantages. For example, a traditional dynamic random access memory (DRAM) cell comprises a capacitor for storing charge representative of a logic ‘0’ or ‘1’ state, and an access transistor for accessing such charge and sending it via a bit line to a sensing circuit. Such a cell design is beneficial in that it can be made relatively dense, and hence many such cells can be placed on a given integrated circuit, amounting in large amounts of memory.

That being said, traditional DRAM cells are not optimal. As just noted, such cells require two elements per cell—the capacitors and the access transistor. While many different DRAM cell designs exist with the goal of reducing the area such cells take up on the surface of an integrated circuit, the reality is that accommodating two elements per cell comprises a significant sizing issue.

In one approach to making smaller memory cells, it has been proposed to use thyristors as the storage element in a memory cell. A thyristor essentially comprises two diodes in series, or what is sometimes referred to as a PNPN structure, which reflects that the device is formed by doping of alternating polarities (P and N). As has been noted in the prior art, thyristor-based cells can be used to selectively store charge, and hence such cells are useable as memory cells. For example, charge can be stored by causing the junctions within the structure to become reversed biased, and such selective storage can be facilitated by gating the thyristor.

However, even thyristor-based memory cell designs are non optimal. Some require or use, in addition to a thyristor gate, an additional access transistor gate for selectively allowing charge transfer between the bit line and the thyristor. Such cell designs therefore suffer from the same drawback as traditional DRAM cells in that they require two devices—an access transistor, and the gated thyristor. In thyristor-based cells not having an access transistor, previous structures still generally take up inordinate amounts of area on the surface of the integrated circuit, for example, because the thyristor is built planar (i.e., horizontally) in the substrate of the integrated circuit. Moreover, such thyristor-based cells not having access transistors have been touted as replacements for traditional SRAM cells, and it is not believed that such cells have been designed as DRAM cells, which are preferable to SRAM cells in many applications. Still other thyristor designs require the device's substrate to be isolated from the bulk substrate, for example, by using a buried oxide (Box) or by using a SOI (silicon-on-insulator) substrate. Using such specialized substrates adds complexity and cost to the manufacture of the thyristor-based cell.

In short, the memory cell art would be benefited from an improved thyristor cell design similar in functionality to a DRAM cell, and such a cell design would be small, would not require additional devices such as access transistors, and would be easily and cheaply manufactured. Embodiments of such a cell design are disclosed herein.

SUMMARY

Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive aspects of this disclosure will be best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a schematic of the disclosed recessed thyristor-based cell.

FIG. 2 illustrates an embodiment of the disclosed recessed thyristor-based cell in cross section.

FIG. 3 illustrates the current-voltage characteristics of the thyristor in the disclosed cell.

FIG. 4 illustrates an array of the disclosed recessed thyristor-based cells, including array driving and sensing circuitry.

FIG. 5 illustrates exemplary voltage conditions for writing a logic ‘0’ or ‘1’ to the disclosed cell, for reading the disclosed cell, and for holding a voltage in the disclosed cell.

FIGS. 6A-6D illustrate an exemplary process for fabricating the disclosed recessed thyristor-based cell.

FIGS. 7A-7C illustrate an exemplary process for fabricating the disclosed recessed thyristor-based cell using epitaxially-grown silicon to form regions of the thyristor.

FIGS. 8A-8B illustrate an exemplary process for fabricating the disclosed recessed thyristor-based cell using junction isolation underneath the cell.

FIG. 9 illustrates an exemplary process for fabricating the disclosed recessed thyristor-based cell using a buried oxide layer or an SOI substrate underneath the cell.

FIG. 10 illustrates an exemplary process for fabricating the disclosed recessed thyristor-based cell using isolation undercuts partially underneath the cell.

DETAILED DESCRIPTION

The improved thyristor-based memory cell 10 is shown schematically in FIG. 1. As can be seen, the cell 10 comprises a thyristor 20, which as noted earlier is a PNPN structure and hence is represented as two serially-connected diodes for ease of illustration. The anode or source of the thyristor 20 (the outer P-region) is coupled to bit line 14. The cathode or drain of the thyristor 20 (the outer N-region) is coupled to a word line 12. The thyristor 20 is gated by an enable gate 16.

As should already be apparent from the schematic of FIG. 1, the cell 10 is simple in design. It requires only a single gate (16), and thus comprises a one-transistor cell, somewhat akin to the access transistor of a traditional DRAM cell, but without a discrete storage capacitor. Moreover, and as will be seen in subsequent Figures, the thyristor 20 portion of the cell is realizable in compact fashion in a traditional semiconductor substrate, e.g., a p-doped substrate. The cell 10 does not require substrate isolation below the cell, although, as will be discussed with reference to FIGS. 8-10, such isolation if used can further improve the performance of the cell and can increase the time needed between refreshes of the cell.

The cell 10 is preferably recessed into the substrate 25, as shown in one embodiment in FIG. 2. Specifically, the enable gate 16 meets with a conductive plug 22 formed in a trench into P-substrate 25. A gate oxide 27 separates the plug 22 from the substrate 25 to allow the thyristor 20 to be gated. As can be seen at the dotted-lined arrow, the thyristor 20 is not planar, but instead is formed vertically formed around the trench in the shape of a “U.” This non-planar configuration further decreases the amount of area that the cell 10 occupies on the substrate 25.

Before discussing the various alternative forms that the recessed thyristor-based cell 10 can take, and before discussing the various ways in which the cell can be fabricated, the operation of the cell is briefly discussed with reference to FIGS. 3 through 5. FIG. 3 shows the principle upon which the thyristor-based cell 10 operates with reference to a current-voltage curve. As this principle is well known, it is only briefly discussed. As shown, when the voltage across the thyristor (Vthy) exceed a certain threshold (Vblock), minority carriers are injected into base (i.e., substrate 25) of the thyristor, and the thyristor enters a period of negative differential resistance, after which the voltage Vthy falls and the current through the thyristor (Ithy) sharply increases. Thus, when Vthy exceeds Vblock, the cell can be said to be programmed to a logic ‘1’ state, and will draw an appreciable current. If Vthy does not exceed Vblock, then the thyristor is not triggered, and the current remains relatively low, i.e., a logic ‘0’ state.

Once the voltages are removed from the device, the cell 10 will retain its charge for a short period of time, perhaps on the order of milliseconds. This occurs due to the depletion region that forms at the PN junctions of the cell. Thus, when programmed via charge injection, the PN junctions will, because of the stored minority-injected charge, be brought into reverse bias, accentuating the depletion regions and their capacitance. This depletion region capacitance stores the minority-injected charge, at least until these minority carrier recombine in the substrate 25. Due to such recombination effects, the thyristor, when used as a cell, may need to be refreshed not unlike a standard DRAM cell.

In any event, after such programming, an operating voltage (Vop) can be placed across the thyristor, and its current monitored to determiner whether the cell had been programmed to a logic ‘1’ (high current) or a logic ‘0’ (low current) state. As one skilled in the art will appreciate, this behavior of the thyristor 20, i.e., its current/voltage characteristics, is preserved even upon application of a small gate voltage (Vgate), such as enable gate 16. Of course, because a more-positive gate voltage will provide additional minority carriers in the P-substrate 25, the voltages needed to program (Vblock) and sense (Vop) will accordingly be reduced with increasing gate voltage.

FIG. 4 shows how the disclosed cells 10 can be situated in a memory array 50, while FIG. 5 illustrates the various voltages that can be used to write a logic ‘1’ or ‘0’, to read the cell, and to hold data in the cell. The array 50 comprises, in one embodiment, bit lines 14 running orthogonally to the enable gates 16 and the word lines 12, but this is merely arbitrary. Additionally, at the edge of the array, and as is typical in memory devices, drivers 30, 32, and 34 are used to respectively drive desired voltages to the bit lines, enable gates, and word lines. Additionally, the bit line driver 30 comprises a sense amplifier which is active when detecting the current/voltage on an active bit line. Such driving and sensing circuits are well known in the art of memory chip design, and could comprise any number of suitable circuits.

FIG. 5 illustrates exemplary voltages that can be used to write, read, and hold the programmed data in the cells 10, and thus comprise the voltages which the drivers 30, 32, 34 will generate under control of an appropriate and typical control circuit (not shown). As can be seen, when writing to the cell, the enable gate 16 is preferably held to ground, but otherwise is held at a negative potential (e.g., −1.0V), an accumulation condition in the P-channel portion of the thyristor 20. When enable gate is grounded during writing, the P-channel region in the thyristor 20 tends towards inversion, with the possibility that Vblock may or may not be exceeded (see FIG. 3). Whether Vblock is exceeded depends on the bit line voltage at the anode relative to the grounded word line voltage on the cathode: if the bit line voltage is also grounded, Vblock is not exceeded, and a logic ‘0’ state is written; if the bit line voltage is high, e.g., Vcc=1.5V, Vblock is exceeded, and the thyristor 20 turns on (i.e., latches) to write a logic ‘1’ state. Once written, the logic state in the cell 10 can be read by sensing the current/voltage on the bit line 14. Reading can occur with the enable gate 16 at the negative potential (e.g., −1.0V) and with the word line grounded. A logic ‘0,’ in which the cell was not charged, fails to perturb the bit line voltage, and as a result, the bit line sense amps will recognize the cell as a logic ‘0’. By contrast, when reading a logic ‘1,’ the stored charge causes the bit line voltage to fluctuate, which the sense amps 30 detect as a logic ‘1.’ During periods in which the cells 10 are neither written to nor read, the data in the cells can be held by holding the word lines and bit lines at Vcc (e.g., 1.5V).

With the operation and architecture of the disclosed recessed thyristor-based cell 10 understood, attention turns to manners in which the recessed thyristor-based cells 10 can be fabricated, starting with a first embodiment shown in FIGS. 6A-6D. FIG. 6A shows two adjacent cells 10 in cross section at an intermediate stage of manufacture. At this stage, several standard processing steps have been performed, and are therefore only briefly summarized. First, a trench 40 has been etched in the P substrate 25. Following growth or deposition of a gate oxide 27, material is deposited for the conductive plug 22, which as noted above will ultimately connect to the enable gate 16. In a preferred embodiment, conductive plug 22 can comprise doped polysilicon, but could comprise other conductive materials used also for substrate plugs, such as tungsten, titanium, silicides, salicides, etc. Following deposition of the conductive plug 22 material, the surface of the substrate 25 can be planarized, such as by Chemical-Mechanical Planarization (CMP) or other known planarization techniques.

In another process step, trench isolation structures 24 are formed around each cell to prevent cross talk between adjacent cells. As is well known, the formation of trench isolation comprises forming a trench 41 in the silicon, filling the trench with a dielectric (e.g., an oxide or nitride), and planarizing the resulting structure. As one skilled in the art will appreciate, the formation of trench isolation structures 24 can also precede the formation of the recessed conductive plug 22, or can be partially concurrent with the formation of the plug, for example, by forming the plug trenches 40 and isolation trenches 41 simultaneously. In any event, the fabrication steps as so far disclosed can occur in many different manners using well known processes.

Next, and as shown in FIG. 6B, the N regions of the thyristor 20 are formed. Forming such regions can comprise a blanket ion implantation in the array of a suitable N-type dopant (e.g., phosphorous or arsenic). As one skilled in the art will appreciate, implantation into the conductive plug 22 and isolation structures 24 will not affect those structures.

Thereafter, a hard mask 43 is deposited, patterned (e.g., with photoresist; not shown), and etched to cover the cathode (i.e., bit line) portions of the thyristor 20. The hard mask 43 can comprise any material suitable as an ion implantation mask, such as nitride. Alignment of the hard mask 43 is eased by the lateral dimensions of the top of the conductive plug 22, and hence this masking step can be performed without strict tolerance.

After formation of the hard mask 43, another ion implantation step is performed to form the P anodes (i.e., bit lines) of the device. As shown in FIG. 6C, after formation of the hard mask 43, the P regions can be formed using a blanket ion implantation in the array of a suitable P-type dopant (e.g., boron), with the hard mask protecting the N-regions at the cathodes. The P doping in this example occurs in a formerly doped N region. However, as illustrated by the arrows in FIG. 6C, the N regions under the newly-implanted P regions are driven downward into the substrate by the “emitter push effect,” which is well known and hence not further discussed. Alternatively, if the N regions were formed deeply enough, the newly-implanted P anode region can be implanted at a shallow depth without need to rely on the emitter push effect.

Thereafter, the hard mask 43 is removed, and standard processing can be used to form the enable gates 16, the word lines 12, and the bit lines 14 into dielectric layers 26 (e.g., oxides), as shown in FIG. 6D. However, after removing the hard mask 43, the exposed tops of the anode and cathode regions of the thyristor 20 can optionally be silicided 31, as shown in FIG. 6D. Such silicidation 31 creates a Schottky barrier, i.e., a potential barrier created at the interface between a metal silicide and a doped semiconductor region. By tailoring the silicidation process, e.g., temperature, materials, phase transformation conditions, etc., the electrical performance of this barrier can be tailored. Because the charge injected into the source and drain depends on this potential barrier, silicidation offers additional options in designing the thyristor characteristics.

Other embodiments for the structure and manufacture of the recessed thyristor-based cell 10 are possible, and some are illustrated in subsequent Figures. First, FIGS. 7A-7C disclose a process for fabricating the recessed cell 10 in which the thyristor is formed in part using epitaxially grown silicon. Starting with FIG. 7A, a pad material 50, such as a nitride, is deposited on the surface of the substrate 25. Thereafter, a trench 40 is drilled through the pad 50 and the substrate. The trench can then be filled with gate oxide 27 and a conductive plug 22 as described earlier. Thereafter, in FIG. 7B, the pad 50 is removed. At this point, the N regions of the thyristor 20 are formed on the surface of the substrate 25, as shown in FIG. 7C. This could be accomplished by ion implantation, or the N regions could be epitaxially grown. After formation of the N regions, a hard mask 52 is formed over the cathode (i.e., bit line) portions of the thyristor 20. This allows the P anode (i.e., word line) to be epitaxially grown on the exposed N region, at which point the thyristor 20 is fully formed. After this, the hard mask 52 is removed, and processing continues to form the word lines, enable gates, and bit lines as discussed above. One skilled in the art will recognize that suitable epitaxial growth processes are well known in the art, and hence are not further discussed.

As noted earlier, isolation under the recessed thyristor-based cell 10 can improve its performance, and particularly can improve its data retention and lengthen the time needed between refreshes. Accordingly, subsequent embodiments disclose ways in which such isolation can be effectuated. For example, in FIG. 8A, the P-doped base of the thyristor (25) is formed within an N substrate 62. In this embodiment, it is preferred that the N-substrate 62 be biased to a high voltage (e.g., to the power supply voltage, Vcc) to ensure that the diode formed between the thyristor base 25 and the N substrate 62 will not be forward biased and hence will be isolated. One skilled in the art will understand that a contact to the N-substrate 62 can be used to provide the appropriate bias, although not shown in the cross section. In another embodiment, shown in FIG. 8B, a P substrate 66 is used, but isolation is formed underneath the base by forming an N well 64, and within that well 64, the P base 25 is formed. Again, the N well 64 would preferably be biased to a high voltage to provide isolation with respect to the P substrate 66 (typically grounded) and the P base 25 of the thyristor 20, although again the contact to establish such a bias is not shown.

Another means for improved isolation of the thyristor is shown in FIG. 9, in which the cell 10 is formed using a buried oxide layer (Box 70). Although not required, it is preferred that the Box layer 70 be rich in a P dopant, such as boron, so that P dopants from the base 25 do not diffuse to the Box layer 70 and negatively affect thyristor 20 performance. One skilled in the art will appreciate that many techniques exist in the art for forming a starting substrate 25 with a Box layer 70, and hence this is not further discussed. Additionally, it should be understood that the Box layer 70 is akin to use of the bulk insulator of an SOI (silicon on insulator) substrate, which would have similar performance to the embodiment shown in FIG. 9, and which comprises yet another embodiment of the disclosed cell.

FIG. 10 illustrates another embodiment of the recessed thyristor-based cell 10 having improved isolation under the cell. In this embodiment, the isolation structures 75 include undercuts 76, which as their name suggests undercut the thyristor 20 in significant part and assists in its isolation. The undercuts 76 can be formed by first creating an anisotropic trench (e.g., trench 41 of FIG. 6A), and then subjecting the trench to a wet etch after the trench has been formed. For example, a wet etch solution of TMAH (Tetra-Methyl Ammonium Hydroxide) can be used to form the undercut 76. Thereafter, the trench and undercut 76 can be filled using a low-pressure oxide vapor deposition process, as is well known, to form the undercutting isolation structures 75 as shown in FIG. 10.

Regardless of whether isolation under the thyristor 20 is used, it should be appreciated that the recessed thyristor-based cell 10 results in a cell design that is compact, easy to manufacture, and easy to form into an array of cells. As a result, the disclosed cells can exhibit improved cell densities when compared to traditional DRAM cells. Specifically, it is believed that the disclosed cell 10 would have particular applicability in embedded DRAM applications, in which volatile cells (requiring refresh) are incorporated into otherwise standard semiconductor chips, such as microprocessors or microcontrollers. In such embedded applications, refresh can occur with greater frequency, and thus even should the disclosed cell 10 require more frequent refresh than traditional DRAM cells, this would not be expected to cause a considerable design constraint. However, it should also be noted that the disclosed cell has applicability in traditional non-embedded integrated circuits as well.

While the thyristor 20 as used in the disclosed cell 10 is disclosed as being a PNPN structure, one skilled in the art will realize that a NPNP structure could be used as well. In such a structure, electrons instead of holes will comprise the majority carriers, but the cell will work equally well assuming that the potentials presented to the cell nodes are of opposite polarity. The ability to use thyristors of differing polarities provides design flexibility, particularly when considering use of the disclosed cell 10 in an embedded application.

It should be understood that the terms “anode” and “cathode” refer merely to the end node terminals of the thyristor, and accordingly that it is irrelevant which of these terminals actually sinks or sources current. Thus, these terms should be understood as interchangeably throughout this disclosure and the claims.

It should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent. 

1. A memory cell, comprising: a conductive plug formed into a substrate; and a thyristor disposed in the substrate and formed vertically around the conductive plug and isolated from the conductive plug by a dielectric.
 2. The memory cell of claim 1, wherein a first node of the thyristor is directly coupled to a bit line in an array, wherein a second node of the thyristor is directly coupled to a word line in the array, and wherein the conductive plug is directly coupled to an enable gate in the array.
 3. The memory cell of claim 1, further comprising a means for isolating the cell formed underneath of the thyristor.
 4. The memory cell of claim 1, further comprising trench isolation formed around the cell.
 5. The memory cell of claim 1, further comprising an isolation structure formed underneath the thyristor in contact with the trench isolation.
 6. The memory cell of claim 5, wherein the isolation structure comprises a buried oxide layer.
 7. The memory cell of claim 5, wherein the isolation structure comprises the bulk insulator of an SOI substrate.
 8. The memory cell of claim 5, wherein the isolation structure comprises a reversed-biased diode.
 9. The memory cell of claim 5, wherein the isolation structure comprises dielectric undercuts.
 10. A memory cell, comprising: a conductive plug formed into a substrate; and a thyristor disposed in the substrate and formed around the conductive plug in a U-shape.
 11. The memory cell of claim 10, wherein a first node of the thyristor is directly coupled to a bit line in an array, wherein a second node of the thyristor is directly coupled to a word line in the array, and wherein the conductive plug is directly coupled to an enable gate in the array.
 12. The memory cell of claim 10, further comprising a means for isolating the cell formed underneath of the thyristor.
 13. The memory cell of claim 10, further comprising trench isolation formed around the cell.
 14. The memory cell of claim 10, further comprising an isolation structure formed underneath the thyristor in contact with the trench isolation.
 15. The memory cell of claim 14, wherein the isolation structure comprises a buried oxide layer.
 16. The memory cell of claim 14, wherein the isolation structure comprises the bulk insulator of an SOI substrate.
 17. The memory cell of claim 14, wherein the isolation structure comprises a reversed-biased diode.
 18. The memory cell of claim 14, wherein the isolation structure comprises dielectric undercuts.
 19. A memory cell, comprising: a conductive plug formed into a trench in a substrate doped to a first polarity, wherein the conductive plug is insulated from the substrate by a dielectric layer; first doped regions along the sides of the trench, wherein the doped regions are doped with a second polarity opposite the first polarity; and a second doped region along only one side of the trench, wherein the second doped region is above one of the first doped regions and is doped to the first polarity.
 20. The memory cell of claim 19, wherein one of the first doped regions is directly coupled to a bit line in an array, wherein the second doped region is directly coupled to a word line in the array, and wherein the conductive plug is directly coupled to an enable gate in the array.
 21. The memory cell of claim 19, further comprising a means for isolating the cell formed underneath of the thyristor.
 22. The memory cell of claim 19, further comprising trench isolation formed around the cell.
 23. The memory cell of claim 19, further comprising an isolation structure formed underneath the memory cell in contact with the trench isolation.
 24. The memory cell of claim 23, wherein the isolation structure comprises a buried oxide layer.
 25. The memory cell of claim 23, wherein the isolation structure comprises the bulk insulator of an SOI substrate.
 26. The memory cell of claim 23, wherein the isolation structure comprises a reversed-biased diode.
 27. The memory cell of claim 23, wherein the isolation structure comprises dielectric undercuts.
 28. A method for forming a memory cell, comprising in no particular order: forming a trench into a substrate doped to a first polarity; forming a conductive plug in the trench having sides, wherein the conductive plug is isolated from the substrates by a dielectric; forming first doped regions along the sides of the trench, wherein the doped regions are doped with a second polarity opposite the first polarity; and forming a second doped region along only one side of the trench, wherein the second doped region is above one of the first doped regions.
 29. The method of claim 28, wherein one of the first doped regions is directly coupled to a bit line in an array, wherein the second doped region is directly coupled to a word line in the array, and wherein the conductive plug is directly coupled to an enable gate in the array.
 30. The method of claim 28, further comprising forming a means for isolating the cell formed underneath of the memory cell.
 31. The method of claim 28, further comprising forming trench isolation around the cell.
 32. The method of claim 28, further comprising forming an isolation structure underneath the memory cell in contact with the trench isolation.
 33. The method of claim 28, wherein at least one of the first regions or the second region is formed by an epitaxial process.
 34. A memory cell array, comprising: a matrix of memory cells, each of the memory cells comprising a conductive plug formed into the substrate, and a thyristor disposed in the substrate and formed vertically around the conductive plug and isolated from the conductive plug by a dielectric, the thyristor comprising first and second nodes; at least one enable gate coupled to the conductive plugs of a plurality of a plurality of the memory cells along a first line; at least one bit line coupled to the first nodes of a plurality of the memory cells along a second line; and at least one word line coupled to the second nodes of a plurality of the memory cells along a third line.
 35. A memory cell array, comprising: a matrix of memory cells, each of the memory cells comprising a conductive plug formed into the substrate, and a thyristor disposed in the substrate and formed around the conductive plug in a U-shape; at least one enable gate coupled to the conductive plugs of a plurality of a plurality of the memory cells along a first line; at least one bit line coupled to thyristor anodes of a plurality of the memory cells along a second line; and at least one word line coupled to thyristor cathodes of a plurality of the memory cells along a third line.
 36. A memory cell array, comprising: a matrix of memory cells, each of the memory cells comprising a conductive plug formed into a trench in a substrate doped to a first polarity, wherein the conductive plug is insulated from the substrate by a dielectric layer, first doped regions along the sides of the trench, wherein the doped regions are doped with a second polarity opposite the first polarity, and a second doped region along only one side of the trench, wherein the second doped region is above one of the first doped regions and is doped to the first polarity; at least one enable gate coupled to the conductive plugs of a plurality of a plurality of the memory cells along a first line; at least one bit line coupled to one of the first doped regions of a plurality of the memory cells along a second line; and at least one word line coupled to the second doped region of a plurality of the memory cells along a third line. 